NVIDIA is hiring for the role of DFT Engineer!
Responsibilities of the Candidates:
Design and implementation of state-of-the-art designs in test access mechanisms, memory BIST, and scan compression.
Carry out the verification and silicon bring-up of Scan ATPG and other DFT features.
Develop and deploy DFT methodologies for our next-generation products.
Work with multi-functional teams to incorporate DFT features into the chip.
Bachelor’s/Master’s degree in Science (Electronic Engineering) from reputed institutions or equivalent experience.
1+ Years of experience preferably in Design for testability (DFT).
Well versed in static timing Analysis, ECO, ASIC/Logic Design Flow, HDL, and Digital logic design.
Experience in RTL and Gates verification and simulation.
Familarity with BIST architecture and JTAG/IEEE1149.1/IEEE1500.
Strong DFT knowledge in Scan ATPG, compression techniques, and memory tests.
Strong analytical and problem-solving skills.
Expert coding skills in industry-standard scripting languages.
Extraordinary written and oral communication skills with the curiosity to work on rare challenges.
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